The present invention relates generally to a receiver with delay generally insensitive to input amplitude and slew rate.
Various arrangements are known for receivers or amplifiers. Differential amplifiers are known for various high-speed applications.
For example, U.S. Pat. No. 5,039,952, issued Aug. 13, 1991 and assigned to the present assignee, discloses an amplifier circuit including first and second gain cells connected in cascade. Each of the gain cells includes first and second common emitter differential transistors, a current source coupled to the emitters of the transistors, a first plurality of forward biased, series diodes connected between a power supply terminal and a base of the first transistor, and a second plurality of forward biased, series diodes connected between the power supply terminal and a base of the second transistor. A collector of the first transistor of the first gain cell is connected to the base of the first transistor of the second gain cell, and a collector of the second transistor of a first gain cell is connected to the base of the second transistor of the second gain cell. Because of the low inherent resistance of the biasing diodes, the operating speed of the amplifier is large, and the current amplification can be large without exceeding the power supply voltage. The current source limits the gain for high level signals without causing saturation of the transistors and therefore, does not comprise operating speed. The gain of each cell equals the numbers of diodes connected to the base of the transistor until the level of the current source.
U.S. Pat. No. 4,914,401, issued Apr. 3, 1990, discloses filters that are controlled and implemented with the aid of a differential gain stage. The differential gain stage includes pairs of like amplification components differential transistor pairs, and groups of series-connected diode components as well as at least one current generator. The forward voltage drop of the diode components has the same current responsiveness as the base-emitter voltage of the amplification components. A filter of the first order includes a differential gain stage with a capacitive component connected across the output of said stage or to its amplification components. A filter of the second order includes two differential gain stages, each with its capacitive component in circuit. An oscillator for controlling filters can comprise three series-connected lowpass filters each including its differential gain stage.
U.S. Pat. No. 5,357,209, issued Oct. 18, 1994, discloses a limiting amplifier having between an amplifier input and an amplifier output at least one amplifier stage as well as load components. The amplifier has an output signal limiting device for limiting the maximum amplitude of the output signal and the amplification and includes a current drain device connected to the amplifier stage output and drawing current through the load components. The amplifier stage includes a differential transistor pair amplifier stage with a differential input and a differential output, two current drain devices being connected to each one of the terminals of the differential output. The load components include a group of series connected diodes formed by NPN transistors with their base and collector electrodes connected together.
A problem with many known arrangements is that the delay of many known receivers is sensitive to changes in the input amplitude and input slew rate. A need exists for a receiver with delay generally insensitive to input amplitude and slew rate. Such a receiver with delay generally insensitive to input amplitude and slew rate is needed in order to minimize the jitter in a system.
A principal object of the present invention is to provide a receiver with delay generally insensitive to input amplitude and slew rate. Other important objects of the present invention are to provide such receiver with delay generally insensitive to input amplitude and slew rate substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.